CDCLVD2108 buffer equivalent, dual 1:8 low additive jitter lvds buffer.
1
* Dual 1:8 Differential Buffer
* Low Additive Jitter <300 fs RMS in
10 kHz to 20 MHz
* Low Within Bank Output Skew of 50 ps (Max)
* Universal Inputs Acc.
* Telecommunications/Networking
* Medical Imaging
* Test and Measurement Equipment
* Wireless Communicat.
The CDCLVD2108 clock buffer distributes two clock inputs (IN0, IN1) to a total of 16 pairs of differential LVDS clock outputs (OUT0, OUT15). Each buffer block consists of one input and 8 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS..
Image gallery
TAGS
Manufacturer
Related datasheet
Download (Size : 1.88MB)